The present invention relates to the use of low temperature deposition of a high K dielectric material with post deposition annealing.
A dynamic random access memory (DRAM) cell typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device, which functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the capacitance, C=epsilonA/d, where epsilon is the dielectric constant of the capacitor dielectric, A is the electrode (or storage node) area and d is the interelectrode spacing. The conditions of DRAM operation such as operating voltage, leakage rate and refresh rate, in general mandate that a certain minimum charge be stored by the capacitor.
The capacitance of a memory cell capacitor is proportional to the surface area A of the opposing electrodes, and proportional to the dielectric constant of the dielectric layer between the opposing electrodes. The capacitance of the memory cell capacitor is inversely proportional to the distance between the opposing electrodes. As dynamic random access memory devices become more highly integrated, space available for each memory cell is reduced, and more particularly, the space available for each memory cell capacitor is reduced. The reduced area available for a capacitor in turn leads to reduced surface area of the opposing electrodes, thereby reducing the capacitance of the memory cell capacitor. Reductions in memory cell capacitance, however, may reduce the performance of the integrated circuit memory device. Accordingly, there exists a need to maintain a predetermined memory cell capacitance despite reductions in memory cell capacitor size.
Three basic techniques have been developed to increase memory cell capacitance without increasing the size of the memory cell capacitor. First, the dielectric layer between the opposing electrodes can be made thinner. Second, a dielectric material having a relatively high dielectric constant can be provided between the opposing electrodes. Third, the surface area of the opposing electrodes can be increased.
Recently, for example, a great deal of attention has been given to the development of thin film dielectric materials that possess a dielectric constant significantly greater ( greater than 10xc3x97) than the conventional dielectrics, such as silicon oxides or nitrides, used in conventional manufacture. Particular attention has been paid to Barium Strontium Titanate (BST), Barium Titanate (BT), Lead Zirconate Titanate (PZT), Tantalum Pentoxide (Ta2O5) and other high dielectric constant materials as a cell dielectric material of choice for DRAMs. These materials, in particular BST, have a high dielectric constant and low leakage currents, which makes them very attractive for high density memory devices.
To be useful dielectrics, the dielectric layers must have proper crystallization to realize the high-K properties. In the case of BST thin films, this is generally achieved by high temperature deposition and annealing of the BST films. Most conventional processes for obtaining favorable BST crystallization require lengthy furnace anneals, and are not very cost effective. In addition, high temperature deposition does not reproducibly provide adequate step coverage of the BST onto the underlying substrate.
There is thus a need in the art for a method of dielectric material deposition that provides both proper crystallization of the dielectric material and adequate step coverage of the substrate.
The present invention provides a means for obtaining high-K dielectric thin films on a substrate, e.g., silicon, by 1) low temperature (500xc2x0 C. or less) deposition of a dielectric material onto a surface, followed by 2) high temperature (over 500xc2x0 C.) post-deposition annealing. The deposition can take place in an oxidative environment, followed by annealing, or alternatively the deposition can take place in a non-oxidative environment (e.g., N2), followed by oxidation and annealing.
In one embodiment, the invention provides a method for manufacturing an electrode using a two-step process for depositing and annealing the dielectric layer of the capacitor. The first step is a low temperature deposition that allows proper step coverage of the bottom electrode, i.e., providing a layer with substantially consistent thickness and conformity over the features forming the bottom electrode. This is then followed by annealing at a high temperature to provide proper crystallization of the dielectric materials, resulting in a layer of material having a high dielectric constant.
In another embodiment, the invention provides a DRAM capacitor having a dielectric layer formed using two-step process to create a high-K dielectric layer having both adequate step coverage and proper crystallization. Preferably, the capacitor is a MIM DRAM capacitor, with a dielectric layer formed between two metal electrodes, preferably, the dielectric layer is barium strontium titanate.
In yet another embodiment, the invention provides a capacitor within a integrated circuit composed of a first electrode, a dielectric layer annealed to said first electrode, and a second electrode covering said dielectric layer. The second electrode may be directly in contact with the dielectric layer, or may be in contact with another layer over said dielectric layer. The dielectric layer is formed using the two-step process to create a high-K dielectric layer having both adequate step coverage and proper crystallization.
In yet another embodiment, the invention provides a method of fabricating a MIM DRAM capacitor by depositing and annealing a dielectric material having a dielectric constant of at least 200-400 onto a platinum film, and covering the dielectric material with a second electrode.
Yet another embodiment of the invention provides a semiconductor device having a capacitor formed on an insulated surface of the semiconductor substrate. The capacitor has a pair of electrodes, with a dielectric layer between the electrodes, preferably a dielectric layer composed of a material having a dielectric constant of at least 300. The dielectric layer is deposited and annealed using the two step process of the present invention. An interconnection layer operatively connects one of the electrodes to the semiconductor integrated circuit.
It is an aspect of the present invention to provide a thin film of a dielectric material such as BST which provides low leakage characteristics for a capacitor of small size and high electrostatic capacity.
It is an object of the invention to provide a suitable substrate for deposition of dielectric materials such as BST.
An advantage of the present invention is that the dielectric layer displays both adequate step coverage and proper crystallization.
An advantage of the present method is that it shortens processing times compared to conventional methods of forming high-K dielectric layers.
Another advantage of the present method is that is conserves thermal budgets.
These and other objects, advantages, and features of the invention will become apparent to those persons skilled in the art upon reading the details of the methods as more fully described below.